1. Field of the Invention
This invention relates to a data processing system interface and in particular to a data processing system having a plurality of individual buses between sub-blocks of the system which are selectively reconfigurable, that is, may be isolated and split to form new independent bus paths, and to a multiple pointer memory system which may be used in conjunction with the plurality of individual buses and the bus splitting means.
2. Description of the Prior Art
Prior data processing systems have utilized a plurality of system buses having fixed data communication paths between logic blocks of the data processing system. However, fixed data transfer paths necessarily restrict microinstruction cycle time in a data processing system. Thus, a data processing operation such as adding the contents of a memory location to the contents in the central processing unit (CPU or ALU-arithmetic logic unit) and storing the resultant operand back in a different memory location has previously required either multiple memory cycles which slows the data processing system throughput, or the use of redundant parallel dedicated fixed position data paths, at a cost of increased layout complexity and more difficult interconnect and space requirements. Additionally, in prior systems, where shared dedicated bus structures are utilized, multiple operations on opposite ends of a common bus structure are not possible since the logic blocks attempting to communicate will compete.
It is therefore an object of the present invention to solve the above enumerated problems and others, and to provide a versatile high speed means of performing multiple memory cycles in a given instruction cycle and for performing simultaneous operations between different logic blocks coupled to a splittable common bus.